Uncertainty Quantification · EDA · Semiconductor Design

CERTAINTYIN EVERYCircuit.

Monte Carlo was invented in 1949. Your 2nm chip deserves better.

QUINSIM replaces brute-force sampling with physics-informed uncertainty quantification that is 1000× faster, captures correlated non-Gaussian process variation, and automatically tells you exactly what is killing your yield.

1000×
Faster than Monte Carlo
5σ
Tail yield confidence
15+
Years research base
The Problem

Monte Carlo
was invented in 1949.

At sub-5nm nodes, process variation is the dominant design risk. Every standard tool in your stack is fighting it with 75-year-old statistics.

Monte Carlo Converges at 1/√N

Getting 5σ confidence on an SRAM cell requires 10⁷ SPICE simulations. At 3 seconds each, that's 347 days of compute — per circuit, per corner.

Your Process Variations Are Not Gaussian

FinFET and GAA threshold voltage distributions are non-Gaussian by physics. Vth in SRAM transistors follows a skewed distribution from line-edge roughness. Every σ value in your PDK is a lie.

Corner Models Miss Correlated Failures

PVT corners assume parameters vary independently. In reality, Tox and Vth are nonlinearly coupled. Your worst-case corner is not the circuit's actual failure mode.

?

No One Knows What Is Killing Your Yield

Conventional tools identify that yield is low. They cannot tell you which of 57 process parameters is responsible, or by how much. QUINSIM can — analytically, from a single run.

Simulation cost to reach 5σ yield confidence
Monte Carlo
10,000,000 samples
QUINSIM sPCE
350 samples
57-parameter 5nm FinFET SRAM SNM benchmark · ICCAD reference
▲ QUINSIM delivers equivalent accuracy in 0.0035% of the simulation budget
How It Works

The UQ Engine
that changes everything.

QUINSIM wraps your existing simulator — Spectre, HSPICE, Eldo, Sentaurus — as a black box. No code changes. No porting. Full statistical intelligence in three steps.

01
📊

Characterize — Non-Gaussian Joint Distributions

QUINSIM ingests foundry measurement data and fits a copula-based joint probability model to your process parameters — capturing non-Gaussian marginals and nonlinear correlations that Gaussian PDK models systematically miss.

Vine Copula · KDE · Rosenblatt Transform
02

Surrogate — Sparse Polynomial Chaos Expansion

From 100–500 adaptive SPICE simulations, QUINSIM builds a mathematical surrogate of your circuit that can be evaluated in microseconds. It achieves the statistical accuracy of millions of Monte Carlo runs at a fraction of the cost.

Sparse PCE · Active Learning · LASSO
03
🎯

Optimize — Sobol-Guided Design Centering

Sobol sensitivity indices — computed analytically from PCE coefficients, zero additional cost — rank every parameter by its contribution to yield loss. QUINSIM then auto-centers your design toward maximum yield.

Sobol Indices · EGO · Yield Surface
Demonstrators

Built for the
hardest circuits.

SRAM Bit-Cell

6T / 8T cell at 5nm FinFET — the broadest commercial pain point

Static Noise Margin (SNM) and write-margin failures at 5σ are the #1 SRAM signoff bottleneck. Cadence Spectre FMC can accelerate, but it is still sampling-based — and still assumes Gaussian distributions that physics violates.

QUINSIM constructs a 57-parameter sparse PCE surrogate from 350 adaptive simulations. The trained surrogate delivers the full 5σ yield surface — probability of failure at every operating point, not just a pass/fail count.

350×
Simulation reduction
350 samples vs. 10M Monte Carlo
4hrs
Full 5σ yield characterization
vs. 347 days Monte Carlo on same hardware
3 params
Dominant failure drivers (Sobol)
Tox, Vth_PMOS, Leff — actionable, not anecdotal

RF LNA / VCO

28nm / 22nm FDSOI — correlated back-gate coupling

FDSOI processes use intentional back-gate biasing for threshold voltage tuning, creating a strong nonlinear coupling between Vth and device operating point that a Gaussian PDK completely fails to model.

QUINSIM employs a Student-t copula for the Vth–DVT0W pair, capturing heavy-tail co-dependence. The result: accurate prediction of a bimodal NF distribution — a capability no conventional UQ tool can achieve.

+15%
Yield improvement identified
Via QUINSIM design centering
Bimodal distribution captured
Monte Carlo misses the second mode entirely
Real
Worst-case corner found
Not a PVT proxy — the actual failure point

High-Speed SAR ADC

ENOB degradation from 80–150 correlated parameters

Effective Number of Bits (ENOB) degradation from capacitor mismatch, comparator offset, and timing jitter is notoriously difficult to characterize — too many correlated parameters for Monte Carlo to explore efficiently.

QUINSIM's high-dimentional structured PCE handles 150-parameter spaces with 600 adaptive samples, delivering full ENOB probability distribution and failure probability per specification.

150 params
Correlated UQ handled
In 8hrs vs. 3-week Monte Carlo campaign
600 sims
Total SPICE calls
For full 6σ ENOB characterization
Full PDF
ENOB distribution output
Not just mean ± sigma — entire density

Automotive Power IC

AEC-Q100 qualification at 100× lower simulation cost

Automotive-grade ICs operating from -40°C to 175°C require exhaustive PVT characterization for AEC-Q100 compliance. The combined process × temperature space makes conventional Monte Carlo economically prohibitive.

QUINSIM extends the parameter space to include temperature as an uncertain dimension, building joint surrogates that deliver automotive-grade qualification in hours, not months.

100×
Cost reduction vs. MC + PVT sweep
AEC-Q100 compliant characterization
215°C
Temperature range modeled
-40°C to 175°C joint process-temp space
Grade 0
Target AEC qualification
Highest automotive operating class

TCAD / GAA Nanosheet

2nm node calibration in 48 hours, with honest uncertainty bounds

TCAD calibration for a new technology node currently takes 2–4 weeks of manual, deterministic iteration. Uncertainty on calibrated model parameters is unknown. Propagation of that uncertainty to circuit SPICE is entirely absent.

QUINSIM's Bayesian calibration engine uses active learning to select TCAD simulation points, fits a posterior distribution over physical model parameters, and propagates uncertainty through the compact model extraction chain into the UQ-PDK.

48hrs
TCAD calibration cycle
vs. 2–4 weeks manual iteration
Full posterior
Model parameter uncertainty
Not a point estimate — a distribution
E2E stack
Process → circuit propagation
Industry's first automated UQ chain
Technology

Built on 15 years
of industrial-grade UQ.

Method 01 · Surrogate

Sparse Polynomial Chaos Expansion

Stochastic spectral method that builds a polynomial surrogate from an adaptive, minimal sample set. LASSO regularization identifies the active basis terms, exploiting physical sparsity in circuit responses.

Ŷ(Z) = Σ_{α∈A} c_α · Ψ_α(Z) where |A| ≪ (d+p)!/(d!p!)
Method 02 · Distribution

Vine Copula + Rosenblatt Transform

Non-Gaussian marginal CDFs combined with R-vine copula dependence models, mapped to independent uniform space via the Rosenblatt transformation — enabling valid PCE construction for real foundry data.

F_X(x₁,…,x_d) = C(F₁(x₁),…,F_d(x_d)) [Sklar's theorem]
Method 03 · Sensitivity

Sobol Variance Decomposition

First-order and total-effect Sobol sensitivity indices computed analytically from PCE coefficients — zero additional simulation cost. Pinpoints which parameters kill yield and by exactly how much.

S_i = Σ_{α: α_i>0,α_{j≠i}=0} c_α² / Σ_{α≠0} c_α²
Method 04 · Optimization

Efficient Global Optimization (EGO)

Kriging-based surrogate optimization using Expected Improvement acquisition functions. Finds yield-maximizing design parameters in fewer than 200 evaluations for 50+ dimensional design spaces.

EI(x) = E[max(f(x) - f*, 0)] [Jones et al. 1998]

Ready to stop
guessing at yield?

Whether you are an analog design team, memory IP vendor, foundry, or investor — we want to hear from you.